1. Field of the Invention
The present invention relates to an IC (Integrated Circuit) memory card and, more particularly, to an IC memory card having an EEPROM (Electrically Erasable Programmable Read Only Memory).
2. Description of the Related Art
An IC memory card is used with, for example, a digital electronic still camera for the purpose of storing picture data representative of scenes picked up by the camera. While an IC memory card for such an application is often implemented by an SRAM (Static Random Access Memory), an EEPROM is advantageous over an SRAM from the cost standpoint. It is desirable, therefore, that an SRAM and an EEPROM be compatible with each other in respect of the interface to a digital electronic still camera.
Japan Electronics Industry Development Association (JEIDA), for example, has recently proposed an Memory Guideline. In the third edition of this Guideline, JEIDA defines a connector having twenty pins. A memory card with an SRAM has eight terminals to input and output data over an 8-bit parallel transfer bus. The eight terminals are used not only to read and write data in the memory chip of the memory card but also to convey the addresses of the memory locations. Therefore, such a memory card has two extra terminals for distinguishing data and addresses, i.e., the distinction is made on the basis of the logical states of the extra terminals. Specifically, when the address of a memory location is constituted by a plurality of bytes, one of the bytes is designated by the combination of the logical states of the two extra terminals.
The memory card with an SRAM has a control circuit therein for controlling the write-in and read-out of the memory chip. On receiving the bytes of an address, the control circuit sets up the address of the memory chip. Thereafter, the control circuit sequentially increments the address of the memory chip in response to a data clock being applied to a clock terminal, thereby reading or writing data in the memory chip. In this manner, the memory card with an SRAM is constructed such that addresses and data fed from an apparatus in which the card is loaded, i.e., a host are written to the memory chip in response to clock pulses also fed from the host.
An IC memory card implemented with an EEPROM would be complicated in respect of data writing operations, compared to the above-stated SRAM type memory card. Assuming model TC58F1OOOP/F/J which is a 1-megabit EEPROM available from Toshiba, Japan, by way of example, it is necessary to input a write command before an address and to input a verify command after data for verification. Specifically, this particular EEPROM has data input/output terminals independent of address input terminals. To write data in the EEPROM, a command for setting up a write mode is applied to the address terminals and data terminals in the period of three clock pulses. In the subsequent clock period, an address and one byte of data are applied to the address terminals and the data terminals, respectively. Thereafter, a verify mode set-up command is inputted to the address terminals and data terminals in the period of three clock pulses in order to set up a verify mode. In the following clock period, the one byte of data is read out for verification. With an EEPROM type IC memory card, therefore, it is impossible to write data therein by inputting the data together with an address in synchronism with a clock, which results in the need for a complicated sequence.
As stated above, a conventional IC memory card with an EEPROM is not compatible with a memory card implemented with an SRAM. Therefore, when an apparatus operable with both of an SRAM type memory card and an EEPROM type memory card is desired, it was a common practice to provide the apparatus with extra functions capable of executing an exclusive sequence for an EEPROM card. This complicated the construction of the apparatus and thereby obstructed the reduction in the size and cost of the apparatus.